Integrated circuit with vertically structured capacitive element, and its fabricating process
US10818669B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 24, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.