Inventor · Sarlat-la-Canéda, FR

Arnaud Regnier

45Patents

5h-index

25Co-inventors

65Inventor score

Filing activity: Jun 17, 2005 → Mar 8, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8901634B2	Nonvolatile memory cells with a vertical selection gate of variable depth	Physics	9	Active
US9224482B2	Hot-carrier injection programmable memory and method of programming such a memory	Electricity	9	Active
US8729668B2	Adjustable resistor	Electricity	6	Active
US7675106B2	Non-volatile reprogrammable memory	Electricity	6	Active
US10818669B2	Integrated circuit with vertically structured capacitive element, and its fabricating process	Electricity	5	Active
US9368215B2	Method for biasing an embedded source plane of a non-volatile memory having vertical select gates	Physics	5	Active
US9406686B2	Memory cell comprising non-self-aligned horizontal and vertical control gates	Electricity	4	Active
US7242621B2	Floating-gate MOS transistor with double control gate	Electricity	4	Expired
US9076878B2	Non-volatile memory with vertical selection transistors	Electricity	4	Active
US9443598B2	Method for programming a non-volatile memory cell comprising a shared select transistor gate	Electricity	4	Active
US9543311B2	Vertical memory cell with non-self-aligned floating drain-source implant	Electricity	3	Active
US10438960B2	Compact non-volatile memory device of the type with charge trapping in a dielectric interface	Electricity	2	Active
US9941369B2	Memory cell comprising non-self-aligned horizontal and vertical control gates	Electricity	2	Active
US10147733B2	Method for forming a PN junction and associated semiconductor device	Electricity	2	Active
US9825186B2	Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor	Electricity	2	Active
US9876122B2	Vertical memory cell with non-self-aligned floating drain-source implant	Electricity	2	Active
US11405223B2	Device of physically unclonable function with transistors, and manufacturing method	Physics	1	Active
US9691866B2	Memory cell having a vertical selection gate formed in an FDSOI substrate	Electricity	1	Active
US11626365B2	Co-integrated vertically structured capacitive element and fabrication process	Electricity	1	Active
US10403730B2	Memory cell comprising non-self-aligned horizontal and vertical control gates	Electricity	1	Active
US11139303B2	Integrated circuit with vertically structured capacitive element, and its fabricating process	Electricity	1	Active
US9653470B2	Individually read-accessible twin memory cells	Electricity	1	Active
US11004785B2	Co-integrated vertically structured capacitive element and fabrication process	Electricity	1	Active
US11081488B2	Integrated circuit with vertically structured capacitive element, and its fabricating process	Electricity	1	Active
US10971633B2	Structure and method of forming a semiconductor device	Electricity	1	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.