Three-dimensional semiconductor memory device and method of fabricating the same
US10818689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Dec 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.