Single event upset immune flip-flop utilizing a small-area highly resistive element
US10819318B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Oct 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.