Barry Britton
39Patents
15h-index
52Co-inventors
84Inventor score
Filing activity: Nov 4, 1992 → Oct 7, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6020755A | Hybrid programmable gate arrays | Electricity | 134 | Expired |
| US5394031A | Apparatus and method to improve programming speed of field programmable gate arrays | Electricity | 71 | Expired |
| US5396126A | FPGA with distributed switch matrix | Electricity | 66 | Expired |
| US5386156A | Programmable function unit with programmable fast ripple logic | Electricity | 58 | Expired |
| US6483342B2 | Multi-master multi-slave system bus in a field programmable gate array (FPGA) | Electricity | 55 | Expired |
| US5381058A | FPGA having PFU with programmable output driver inputs | Electricity | 51 | Expired |
| US6472904B2 | Double data rate input and output in a programmable logic device | Electricity | 49 | Expired |
| US7385417B1 | Dual slice architectures for programmable logic devices | Electricity | 43 | Active |
| US6043677A | Programmable clock manager for a programmable logic device that can implement delay-locked loop functions | Electricity | 42 | Expired |
| US5311080A | Field programmable gate array with direct input/output connection | Electricity | 39 | Expired |
| US6064225A | Global signal distribution with reduced routing tracks in an FPGA | Electricity | 25 | Expired |
| US6873187B1 | Method and apparatus for controlling signal distribution in an electronic circuit | Electricity | 24 | Expired |
| US5384497A | Low-skew signal routing in a programmable array | Electricity | 24 | Expired |
| US6216191A | Field programmable gate array having a dedicated processor interface | Physics | 24 | Expired |
| US6028463A | Programmable clock manager for a programmable logic device that can generate at least two different output clocks | Electricity | 16 | Expired |
| US7650545B1 | Programmable interconnect for reconfigurable system-on-chip | Physics | 10 | Active |
| US7034596B2 | Adaptive input logic for phase adjustments | Electricity | 9 | Expired |
| US5623217A | Field programmable gate array with write-port enabled memory | Electricity | 9 | Expired |
| US5528170A | Low-skew signal routing in a programmable array | Electricity | 8 | Expired |
| US6060902A | Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device | Electricity | 7 | Expired |
| US7554357B2 | Efficient configuration of daisy-chained programmable logic devices | Physics | 7 | Active |
| US6049224A | Programmable logic device with logic cells having a flexible input structure | Electricity | 4 | Expired |
| US7592834B1 | Logic block control architectures for programmable logic devices | Electricity | 4 | Active |
| US7863931B1 | Flexible delay cell architecture | Electricity | 4 | Active |
| US7599457B2 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.