ECC proxy extension and byte organization for multi-master systems
US10824505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example multi-master system in a system-on-chip (SoC) includes a plurality of master circuits, an error-correcting code (ECC) proxy bridge comprising hardened circuitry in the SoC, a local interconnect configured to couple the plurality of master circuits to the ECC proxy bridge, a memory not having ECC support, and a system interconnect configured to couple the ECC proxy bridge to the memory. The ECC proxy bridge is configured to establish an ECC proxy region in the memory and, for each write transaction from the plurality of master circuits that targets the ECC proxy region, calculate and insert ECC bytes into the respective write transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.