Device for implementing artificial neural network with flexible buffer pool structure
US10824939B2 · kind B2 · utility
14Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2017 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, a data reading scheduling unit and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.