Non-volatile memory with reduced data cache buffer
US10825526B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Jun 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.