Method of erasing data in nonvolatile memory device by changing level of voltage and duration of time to apply the voltage for target erase block
US10825530B2 · kind B2 · utility
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8References
20Claims
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Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.