Multi-die integrated circuits with improved testability
US10825745B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.