Semiconductor device with multi-layered wiring and method for fabricating the same
US10825766B2 · kind B2 · utility
1Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.