Electrostatic protection circuit, array substrate, display panel and display device
US10825807B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 3, 2017 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrostatic protection circuit, an array substrate, a display panel and a display device are disclosed. The electrostatic protection circuit is located within a peripheral region of an array substrate and includes: a first ground wire provided in a same layer as a source electrode and a drain electrode of a thin film transistor located within a display region of the array substrate; and a second ground wire provided in a same layer as a gate electrode of the thin film transistor, wherein, the first ground wire forms a first loop with a printed circuit board provided within the peripheral region, the first loop surrounds the display region; the second ground wire forms a second loop with the printed circuit board, and the second loop surrounds the display region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.