Patent · US Active

PVT-independent fixed delay circuit

US10826473B2 · kind B2 · utility

1Cited by

2References

3Claims

0Family size

Assignee

INTEGRATED SILICON SOLUTION, INC. BEIJING · CN

Inventors

Weikang Liu · Beijing, CN
Chia-Yu Lin · New Taipei, TW

Key dates

Filing date	Dec 5, 2019
Grant date	Nov 3, 2020
Priority date	—
Expiry date	Dec 5, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00202
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.