Fractional divider with error correction
US10826507B1 · kind B1 · utility
7Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | May 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.