Patent · US Active

Systems and methods for cascading radar chips having a low leakage buffer

US10830868B2 · kind B2 · utility

0Cited by

2References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Hao Li · Poing, DE
Herbert Knapp · Munich, DE

Key dates

Filing date	Feb 2, 2018
Grant date	Nov 10, 2020
Priority date	—
Expiry date	Dec 29, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG01S13/931
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.