Lithographic overlay correction and lithographic process
US10831110B2 · kind B2 · utility
1Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jun 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/682
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method includes receiving a wafer, defining a plurality of zones over the wafer, performing a multi-zone alignment compensation for each of the plurality of zones according to an equation along a first direction to obtain a plurality of compensation values for each of the plurality of zones, and performing a wafer alignment and a lithography exposure for each of the plurality of zones according to the plurality of compensation values. The wafer alignment and the lithography exposure are performed zone-by-zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.