Most favored branch issue
US10831492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Nov 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.