Inventor · Austin, TX, US

Salma Ayub

26Patents
3h-index
28Co-inventors
55Inventor score

Filing activity: Jan 13, 2015 → May 4, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US11144319B1 Redistribution of architected states for a processor register file Physics 13 Active
US9740620B2 Distributed history buffer flush and restore handling in a parallel slice design Physics 4 Active
US9747217B2 Distributed history buffer flush and restore handling in a parallel slice design Physics 3 Active
US10133576B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 2 Active
US10949213B2 Logical register recovery within a processor Physics 1 Active
US10120693B2 Fast multi-width instruction issue in parallel slice processor Physics 1 Active
US10613868B2 Variable latency pipe for interleaving instruction tags in a microprocessor Physics 0 Active
US10649779B2 Variable latency pipe for interleaving instruction tags in a microprocessor Physics 0 Active
US11360779B2 Logical register recovery within a processor Physics 0 Active
US11941398B1 Fast mapper restore for flush in processor Physics 0 Active
US10942745B2 Fast multi-width instruction issue in parallel slice processor Physics 0 Active
US11188332B2 System and handling of register data in processors Physics 0 Active
US11068267B2 High bandwidth logical register flush recovery Physics 0 Active
US11150907B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 0 Active
US9996359B2 Fast multi-width instruction issue in parallel slice processor Physics 0 Active
US12061909B2 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Physics 0 Active
US12204902B2 Routing instruction results to a register block of a subdivided register file based on register block utilization rate Physics 0 Active
US11531548B1 Fast perfect issue of dependent instructions in a distributed issue queue system Physics 0 Active
US10255071B2 Method and apparatus for managing a speculative transaction in a processing unit Physics 0 Active
US10831492B2 Most favored branch issue Physics 0 Active
US10248421B2 Operation of a multi-slice processor with reduced flush and restore latency Physics 0 Active
US10740107B2 Operation of a multi-slice processor implementing load-hit-store handling Physics 0 Active
US10445100B2 Broadcasting messages between execution slices for issued instructions indicating when execution results are ready Physics 0 Active
US11561794B2 Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry Physics 0 Active
US10241790B2 Operation of a multi-slice processor with reduced flush and restore latency Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.