Integrated circuit design with optimized timing constraint configuration
US10831958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generating a design of an integrated circuit by analyzing a physical design of an integrated circuit by determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin, determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value, determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin, setting the current timing constraint equal to the candidate timing constraint, and generating a revised physical design of the integrated circuit that incorporates the current timing constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.