Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array
US10832371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Dec 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.