Non-volatile in-memory computing device
US10832746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 1, 2015 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jan 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.