Patent · US Active

Global bit line latch performance and power optimization

US10832763B2 · kind B2 · utility

0Cited by

5References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Martin Bernhard Schmidt · Stuttgart, DE
Harry Barowski · Balingen, DE
Alexander Fritsch · Eßlingen, DE
Matthias Hock · Holzgerlingen, DE

Key dates

Filing date	Dec 18, 2018
Grant date	Nov 10, 2020
Priority date	—
Expiry date	Dec 18, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.