Multi-level micro-device tethers
US10832935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Aug 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.