Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts
US10833257B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | May 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.