Streaming editor circuit for implementing a packet deparsing process
US10834241B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/166
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.