Asynchronous FIFO buffer for redundant columns in memory device
US10838726B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Nov 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.