Device and method for cache utilization aware data compression
US10838727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.