Parallel slice processor shadowing states of hardware threads across execution slices
US10838728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jan 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.