Interactive compilation of software to a hardware language to satisfy formal verification constraints
US10839124B1 · kind B1 · utility
2Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jun 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.