Circuit layout similarity metric for semiconductor testsite coverage
US10839133B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | May 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.