Self-timed memory with adaptive voltage scaling
US10839865B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Apr 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.