Amit Chhabra
33Patents
4h-index
47Co-inventors
59Inventor score
Filing activity: Jun 14, 2010 → Nov 3, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9396790B1 | Multi-supply dual port register file | Physics | 37 | Active |
| US9390786B2 | Method of minimizing the operating voltage of an SRAM cell | Electricity | 5 | Active |
| US9543044B2 | System and method for improving memory performance and identifying weak bits | Physics | 4 | Active |
| US10979303B1 | Segmentation of maintenance on distributed systems | Electricity | 4 | Active |
| US11521400B2 | Systems and methods for detecting logos in a video stream | Physics | 4 | Active |
| US8458545B2 | Method and apparatus for testing of a memory with redundancy elements | Physics | 2 | Active |
| US9659933B2 | Body bias multiplexer for stress-free transmission of positive and negative supplies | Electricity | 2 | Active |
| US10715148B1 | Transient sensing circuitry | Electricity | 2 | Active |
| US9728232B2 | System and method for automatic detection of power up for a dual-rail circuit | Electricity | 2 | Active |
| US11069424B2 | Sensor for performance variation of memory read and write characteristics | Physics | 1 | Active |
| US11093409B1 | Using emulation of storage characteristics to perform an access request translated between different protocols | Physics | 1 | Active |
| US11418851B1 | Virtual set top | Electricity | 1 | Active |
| US9559665B2 | Ultra-low voltage temperature threshold detector | Electricity | 1 | Active |
| US9898894B2 | Method of managing a lottery | Physics | 1 | Active |
| US9378779B2 | System and method for automatic detection of power up for a dual-rail circuit | Electricity | 1 | Active |
| US12165737B2 | Multi-bitcell structure with shared read port | Physics | 0 | Active |
| US10964379B2 | Ring oscillator based bitcell delay monitor | Electricity | 0 | Active |
| US11704977B2 | Method and apparatus for dispensing funds in a lottery | Physics | 0 | Active |
| US12040232B2 | Multi-transistor stack architecture in a single vertical stack | Electricity | 0 | Active |
| US12035517B2 | Multi-transistor stack bitcell architecture | Electricity | 0 | Active |
| US11495499B2 | Method of forming multi-stack transistors in a single semiconductor die | Electricity | 0 | Active |
| US11114154B2 | Voltage retention techniques | Electricity | 0 | Active |
| US11418856B2 | Systems and methods for video content security | Electricity | 0 | Active |
| US11645211B2 | Augmenting storage functionality using emulation of storage characteristics | Physics | 0 | Active |
| US8381049B2 | Apparatus and method for testing shadow logic | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.