Power on reset method for resistive memory storage device
US10839899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Nov 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.