Patent · US Active

In memory computing (IMC) memory circuit having 6T cells

US10839906B2 · kind B2 · utility

0Cited by

6References

15Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventor

Adam Makosiej · Grenoble, FR

Key dates

Filing date	Sep 30, 2019
Grant date	Nov 17, 2020
Priority date	—
Expiry date	Sep 30, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memory circuit for implementing logic operations and provided with memory cells, in particular of structure 6T, with a control circuit configured to activate the first access transistors or the second access transistors of at least two cells of the same given column and for detecting from a low- or high-voltage power supply line, from said given column, separate from the bit lines, a signal representative of the result of a logic operation having for operands data stored in said at least two cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.