Semiconductor memory device with improved threshold voltage distribution of transistor
US10839926B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | May 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.