Selectively etched self-aligned via processes

US10840138B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Yung-Chen Lin · Los Angeles, US
• Qingjun Zhou · Sunnyvale, US
• Ying Zhang · Santa Clara, US
• Ho-yung David Hwang · Hsinchu, TW

Key dates

• Filing date: Sep 17, 2018
• Grant date: Nov 17, 2020
• Expiry date: Sep 17, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76883
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.