Resistive random access memory circuit
US10840299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Sep 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.