Semiconductor device
US10840332B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | Jan 16, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.