Method for void reduction in solder joints
US10843284B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2015 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process to connect, by soldering, at least one electronic component (104, 204, 304, 404, 504) with a mounting plate (100, 200, 300, 400, 500), the mounting plate having at least one mounting plate contact surface (102, 202, 302, 402, 502) and the at least one electronic component having at least one component contact surface (105) corresponding to it, the at least one mounting plate contact surface being surrounded by a solder resist layer (101, 201, 301, 401, 501) that borders the at least one mounting plate contact surface, the process having the following steps: a) Applying solder paste (106, 206, 306, 406, 506) onto at least areas of the solder resist layer (101, 201, 301, 401, 501), minimally overlapping with the mounting plate contact surface (102, 202, 302, 402, 502) adjacent to the solder resist layer, b) Equipping the mounting plate with the at least one electronic component (104, 204, 304, 404, 504), the at least one component contact surface (105) at least partly covering the at least one mounting plate contact surface (102, 202, 302, 402, 502) corresponding to it; and c) Heating the solder paste (106, 206, 306, 406, 506) to produce a soldered …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.