Patent · US Active

Techniques to control an insertion ratio for a cache

US10845995B2 · kind B2 · utility

1Cited by

5References

29Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Yipeng Wang · Houston, US
Ren Wang · Portland, US
Sameh Gobriel · Hillsboro, US
Tsung-Yuan C. Tai · Portland, US

Key dates

Filing date	Jun 30, 2017
Grant date	Nov 24, 2020
Priority date	—
Expiry date	Mar 25, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/502
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.