Unified logic for aliased processor instructions
US10846089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Sep 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.