Performance debug for networks
US10846201B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Dec 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are techniques for debugging the performance of a neural network. In one embodiment, a neural network processor includes a processing engine, a debugging circuit coupled to the processing engine, and an interface to a memory device. The processing engine is configured to execute instructions for implementing a neural network. The debugging circuit is configurable to determine, for each instruction in a set of instructions, a first timestamp indicating a start time of executing the instruction and a second timestamp indicating an end time of executing the instruction by the processing engine. The interface is configured to save the first timestamp and the second timestamp for each instruction in the set of instructions into the memory device. The debugging circuit can be configured to different debug levels. The neural network processor can include multiple debugging circuits for multiple processing engines that operate in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.