Managing translation lookaside buffer entries based on associativity and page size
US10846239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.