Semiconductor devices and fabrication methods thereof

US10847425B2 · kind B2 · utility

Assignees

• Semiconductor Manufacturing International (Beijing) Corporation · CN
• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Yi-Chun Lu · New Taipei, TW
• Changyong Xiao · New York, US
• Yihui Lin · 龙王头村, CN
• Qin Zhang · Beijing, CN
• Hua Wang · Shanghai, CN
• Xiang Hu · Shanghai, CN
• Xiaona Zhu · Shanghai, CN
• Ying Jiang · Raleigh, US

Key dates

• Filing date: Jul 15, 2019
• Grant date: Nov 24, 2020
• Expiry date: Jul 15, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/013
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating a semiconductor device includes forming a plurality of gate structures, a source/drain doped layer, a barrier layer, and a dielectric layer on a base substrate. The barrier layer covers the entire top surfaces of the plurality of gate structures. The dielectric layer covers the source/drain doped layer, the barrier layer, and the gate structures. The method further includes forming a plurality of first vias in the dielectric layer on both sides of each gate structure above the source/drain doped layer; forming a plurality of second vias on the gate structures to expose the barrier layer; performing a pre-amorphizing implantation process on the surface of the source/drain doped layer at the bottom of the first vias; removing the barrier layer at the bottom of the second vias; and forming a metal silicide layer on the surface of the source/drain doped layer through a metal silicidation process.