Compact wirebonding in stacked-chip system in package, and methods of making same
US10847450B2 · kind B2 · utility
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1References
9Claims
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Key dates
| Filing date | Sep 28, 2016 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.