Semiconductor devices with nanowires and methods for fabricating the same
US10847515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Dec 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.