Method and related apparatus for improving memory cell performance in semiconductor-on-insulator technology
US10847575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Aug 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.