Field effect transistor and method of forming the same
US10847634B2 · kind B2 · utility
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10References
20Claims
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Assignee
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Key dates
| Filing date | Jan 31, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.