Method and system for detecting clock failure
US10848140B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2020 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Jul 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.