Performing at least two branch predictions for non-contiguous instruction blocks at the same time using a prediction mapping
US10853076B2 · kind B2 · utility
1Cited by
8References
12Claims
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Key dates
| Filing date | Feb 21, 2018 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Jul 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided to perform branch prediction in respect of a plurality of instructions divided into a plurality of blocks. Receiving circuitry receives references to at least two blocks in the plurality of blocks. Branch prediction circuitry performs at least two branch predictions at a time. The branch predictions are performed in respect of the at least two blocks and the at least two blocks are non-contiguous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.